The present invention relates generally to testable integrated circuits and, in particular, to a method for generating a clock signal in a testable integrated circuit.
Today's integrated circuits include hundreds of thousands of transistors, which form various logic elements such as adders, multipliers, buffers, registers, etc. All of these transistors must be tested to ensure that the integrated circuit will function according to its intended purpose. Due to the large numbers of transistors and high design costs, integrated circuits must be designed for test (DFT). Specific design approaches have evolved to make devices more readily testable, such as Built in Self Test (BIST) and scan testing. Scan testing aims to achieve total or near total controllability and observability in sequential circuits. In scan testing, circuit elements are linked together in one or more chains and then a test pattern is clocked (passed) though the chain. If the output pattern matches the input pattern, it can be deduced that the circuit elements do not contain faults.
As the functional requirements for integrated circuits have become more demanding, the requirements to be met by the clock controller module of the IC have become very stringent. A typical clock controller may be required to process the clocks from multiple PLLs, generate clocks for the core, bus master and slaves, and generate baud clocks for peripherals like USB, SSI, image processor, UART, multimedia card, camera sensor, GPS, etc. The clock controller must also control the clocks during Dynamic Voltage Frequency Scaler (DVFS) and low power modes, and generate chopped clock patterns for at-speed scan testing. In order to meet these demands, multiple clock dividers and multiplexers are used, such that traditional techniques used for clock balancing are impacting design time and chip performance.
FIG. 1 shows a typical clock tree of an integrated circuit 10. The circuit 10 includes multiple dividers, such as DVFS divider 12, core divider 14, Advanced High Performance Bus (AHB) divider 16, and IP divider 18. A test clock (test_clock) is multiplexed with the functional clocks (p110, p111, p112, and p113) via muxes 20, 24, 26, 28, 30 and 32. These muxes are used to differentiate between the functional clocks and the test clock before the respective clock dividers 12-18 for test purposes. The addition of so much test circuitry adds to the clock latency and power consumption, and also to the difficulty in balancing the clock latency, which increases the design cycle. Furthermore, bypassing of clock circuitry during scan makes it difficult to test the clock generation logic.
Referring to FIG. 2, a conventional clock divider circuit 40 used in an integrated circuit is shown. The clock divider circuit 40 includes first and second flip-flops 42 and 44, a plurality of buffers 46, and first and second selectors 48 and 50. An input clock signal, clock_in, is input to the clock divider circuit 40 and provided to the clock inputs of the first and second flip-flops 42 and 44, and also as a data input by way of a pair of the buffers 46 to the first selector 48. The other data input to the first selector 48 is the output of the second flip-flop 44, by way of a pair of the buffers 46. The data output of the first flip-flop 42 is provided, by way of a pair of the buffers 46, to the address or control input of the first selector 48. Thus, the first selector 48 outputs either a buffered clock signal or a divided clock signal. The second selector 50 receives as data inputs the output of the first selector 48 and a test_clock signal. One of the output signals of the first selector 48 and the test_clock signal are selected by the second selector 50 depending on a scan_mode signal. Thus, in scan mode, the test_clock is selected and in normal mode, the clk_out signal is selected.
While the clock divider circuit 40 functions adequately, the second selector 50 increases clock latency. In addition, the test coverage afforded by the divider circuit 40 is less than adequate because the buffers 46 are bypassed. Thus, the buffers 46 and the first selector 48 are not testable.
It would be desirable, at least for components such as SOCs, to provide a clock divider circuit that is tested as comprehensively as possible.